1. Field of the Invention
The technology described in this patent application relates generally to superscalar and VLIW processing optimization, and in particular to the use of programmed logic to assist branch efficiency in superscaler processors.
2. Related Art
Many embedded applications, especially in video compression, require continual iterations of decision trees. The processing of decision trees is often inefficient because it is not possible to know which instruction branch will be taken until the branch conditions are evaluated. This uncertainty prevents multi-stage pipeline processors from fully realizing the increased efficiencies of their design because the pipeline must be flushed if the correct instructions are not following the branch instruction, and the correct instructions can not be determined until the branch instruction is evaluated.
Existing solutions for aiding the efficiency of branch processing include software predictive branch algorithms as well as utilization of dedicated hardware. In some cases predictive branching is effective in alleviating the problem. However, if the prediction is poor or the branches are equally likely and frequent, there is only so much that can be gained and efficiency remains low. Dedicated hardware solutions are very efficient in aiding efficiency when the structure and branching conditions are known prior to runtime. However, for branch intensive algorithms, where branch conditions are not constant or are too numerous to devote hardware to for each set, a dedicated hardware solution may be inappropriate.